Both. The differences are not that great. I don't believe anyone who says they can done something in one that can't be done in another, they just don't now how to do it. After staring at a large design day after day, it is a pleasure to switch to the other one just to break up monotony. If you inherit someone else's design, I prefer to have the component list in VHDL to get an overall picture of what is going on. I guess it is easier to write Verilog, but easier to read someone else's VHDL.