Intel Discontinues the Intel Developer Forum; IDF17 Cancelled

Re:Intel Discontinues the Intel Developer Forum; IDF17 Cance... by adrianratnapala on Tuesday April 18, 2017 @01:28AM (#14136698)

But is RISC the solution to that problem? Having lots of registers helps, I guess. But the amd64 already has quite a lot.

These problems seem to be what VLIW architectures like tried to to solve. Is that sort of architecture going to make a comeback? Will even that help?

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Re:Intel Discontinues the Intel Developer Forum; IDF17 Cance... by rbanffy on Tuesday April 18, 2017 @07:56PM (#14144221)

> But the amd64 already has quite a lot.

16 registers is not a lot when compared to other architectures. POWER, SPARC, Arm64 and MIPS have 32 (SPARC is weird, but 32 are always visible). Itanium has 128.

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Re:Intel Discontinues the Intel Developer Forum; IDF17 Cance... by luca_ing on Thursday April 20, 2017 @07:09AM (#14155650)

I'm far from an expert on CPU architectures, but I suppose there are diminishing returns. Most of my functions use less than 16 values, and those that do may well iterate over more than 128.

Also you're probably aware that modern CPUs have many more physical registers, they just don't expose them all at the same time.

E.g. AMD Zen physically has 168 integer and 160 floating-point registers. Of which you can only use 16 at a time, but to my uninformed eye that looks like a reasonable trade-off.

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