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A comment on An In-Depth Look at Google's Tensor Processing Unit Architecture. Parent comment

Re:An In-Depth Look at Google's Tensor Processing Unit Archi... by pavanky on Wednesday April 05, 2017 @01:19PM (#14043751)
Those limitations sounds awfully similar to that of an FPGA..
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Re:An In-Depth Look at Google's Tensor Processing Unit Archi... by vvanders on Wednesday April 05, 2017 @01:22PM (#14043780)
I was going to say as well. It seems like if caches are the bane of sequential processing(CPU) then routing has to be the counterpart on the parallel(FPGA/ASIC) side of the equation.
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