That's not a very accurate analogy, since sequential reads do improve. CAS latency is one limiting factor on random reads, which has been constant / only slightly improving for a very long time; significant improvements last happened here around with DDR and SDR (i.e. 20 years ago).

This is a central reason why the cache size per thread has not changed much in the last 20 years (beside of course fabbing/yield limits). (And because caches are subject to a similar effect as Dennard scaling)

(btw. I wonder if it'd have been smarter by the memory industry if they specified latencies in absolute numbers (or relative to the memory array clock, not the bus clock), not bus cycles, since the rising latency numbers have been a marketing issue in every generation.)

If cas latency haven't changed for 20 years, and the memory wall in general being a huge pain, does anybody know why didn't some sort of 2.5D memory(even using low-resolution lithography and carriers cheaper than silicon), haven't entered the market ?

Heat, RAM puts out a lot more than you might think. That said, for low power devices like cellphones you can use different packaging and cut latency.

Also, AMD for example uses stacked ram (HBM), but that needs very special packaging and active cooling. http://www.amd.com/en-us/innovations/software-technologies/h... https://en.wikipedia.org/wiki/High_Bandwidth_Memory

If heat is the problem, and since the memory wall is a 20-year problem, was there some new cooling tech ? or is it just standard industry inertia(and just being satisfied with half solutions) ?

No, it's a fundamental issue with the technology. Roughly, the ratio of power density to capacity-that-can-hold-information-for-a-refresh-interval stays more or less constant, independent of fab node. In fact, newer generations (DDR3, DDR4) have been pushing it here (cf. rowhammer).

I doubt we will see a drastic improvement in DRAM latency unless the underlying process changes a lot (i.e. different physical storage mechanism or very different manufacturing).

I think that's what HBM tries to do, with stacking memory dies on top of each other, along with locating them next to its associated processor.