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Re:CPU cache-based communication between two co-located virt... by j_s on Thursday March 30, 2017 @01:41PM (#13997355)
Yes it was specifically called out in someone's tweet I'm trying to find but I believe this was mentioned in the paper.

Edit: My mix-up on the paper!

Malware Guard Extension: Using SGX to Conceal Cache Attacks (Extended Version) | https://arxiv.org/pdf/1702.08719.pdf (2017)

Recently, Intel introduced an instruction set extension called CAT (cache allocation technology) [51]. With Intel CAT it is possible to restrict CPU cores to one of the slices of the last-level cache and even to pin cache lines. Liu et al. [83] proposed a system that uses CAT to protect general purpose software and cryptographic algorithms. Their approach can be directly applied to protect against a malicious enclave. However, this approach also does not allow to protect enclaves from an outside attacker.

[...]

Instead of using Intel CAT on the operating level it could also be used to protect enclaves on the hardware level. By changing the eenter instruction in a way that it implicitly activates CAT for this core, any cache sharing between SGX enclaves and the outside as well as co-located enclaves could be eliminated. Thus, SGX enclaves would be protected from outside attackers. Furthermore, it would protect co-located enclaves as well as the operating system and user programs against malicious enclaves.

[83] https://www.researchgate.net/profile/Yuval_Yarom/publication...

Re:CPU cache-based communication between two co-located virt... by brendangregg on Thursday March 30, 2017 @01:51PM (#13997433)
this paper? https://cmaurice.fr/pdf/ndss17_maurice.pdf where is IntelCAT mentioned?