Re:ARM Launches DynamIQ: big.Little to Eight Cores Per Cluster
by brianwawok on Tuesday March 21, 2017 @11:48AM
(#13923277)
Couldn't you engineer the little core to take the fat instruction it can't process and instead do many small instructions to get the same end result? I am specifically thinking of AVX here, and it seems like it would work.. but perhaps there are other instructions that would not be so easy to unroll.
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Re:ARM Launches DynamIQ: big.Little to Eight Cores Per Cluster
by Symmetry on Tuesday March 21, 2017 @11:59AM
(#13923395)
In terms of AVX breaking up 256-bit vector instructions into two 128-bit vectors is something that's very possible and is, in fact, what AMD is doing in Ryzen. That saves you on execution and datapath silicon but you still need the full sized registers to hold the data and that means that adding AVX to an Atom processor would require a redesign of the back end. And other new instructions might require other backend changes. And to interpret new instructions you certainly have to make silicon changes to the front end which might have follow on effects on the general layout.
But in general you could certainly design an Atom-ish core that has the full range of Intel instructions. Or just add AVX (they've already done this with Phi) and take all the other extra instructions out of the SKylake.