ARM Launches DynamIQ: big.Little to Eight Cores Per Cluster

Re:ARM Launches DynamIQ: big.Little to Eight Cores Per Cluster by microcolonel on Tuesday March 21, 2017 @09:58AM (#13922209)

This is one of those interesting cases where RISC-V could eat their (and maybe ARM's) lunch on implementations like this. The wide vector instructions (i.e. not the packed SIMD, but the -V extension) are width-independent, so you could just make the vector machine narrower on the little core, and switch it to low-frequency in-order.

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Re:ARM Launches DynamIQ: big.Little to Eight Cores Per Cluster by Symmetry on Tuesday March 21, 2017 @10:23AM (#13922401)

ARM recently added a similar wide vector instruction called SVE which works similarly. But yes, that way of doing vectors is really cool.

EDIT: Come to think of it, this might be something ARM has been adding deliberately partially to be able to use hetrogenous cores.

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Re:ARM Launches DynamIQ: big.Little to Eight Cores Per Cluster by pertymcpert on Wednesday March 22, 2017 @06:41AM (#13929846)

ARM did it first with SVE. The RISC-V vector extension is just a draft while I believe SVE silicon is being developed now for exascale HPC.

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Re:ARM Launches DynamIQ: big.Little to Eight Cores Per Cluster by microcolonel on Wednesday March 22, 2017 @11:35PM (#13937229)

Cray did it first, that's why there's no patent dispute right now.

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