Re:What happened to clockless computer chips?
by kruhft on Monday February 27, 2017 @04:57PM
(#13748670)
> synchronous logic design because everything happens in parallel, but it's a set of well-understood building blocks. Whereas asynchronous design is just entirely free of familiar reference points and there isn't quite the same set of standard idioms....Yes, you get rid of setup/hold violations, but you're going to get a whole new class of problems with the addition that "timing closure" is now a moving target.
Sounds like the argument about the problems and differences typed/untyped programming languages. One set of problems is solved with typing at the cost of linguistic expressiveness due to lacking and/or cumbersome type systems.
I'm thinking async hardware is the typeless of HW designs, but that also takes off the safety guards used from years of experience in synchronous design.
This reminds me of 4GL hype.
I'd say it's the other way round. People have trouble learning synchronous logic design because everything happens in parallel, but it's a set of well-understood building blocks. Whereas asynchronous design is just entirely free of familiar reference points and there isn't quite the same set of standard idioms.
Yes, you get rid of setup/hold violations, but you're going to get a whole new class of problems with the addition that "timing closure" is now a moving target.
Async design in simulation is not some great hidden secret, it's just a trackless jungle. People are welcome to play with it; if you find a great way of teaching async design I'm sure we'd all like to hear about it.