A small Lisp-Machine in an FPGA

Re:A small Lisp-Machine in an FPGA by e19293001 on Saturday February 11, 2017 @10:59AM (#13623136)

The verilog code had been poorly written. For example, it's not common for a combinational circuit to have an input reset. Latches are inferred in some places that can cause unexpected behavior. That's just my observation though. It's cool to see projects like this. Sadly, it appears to be inactive after seeing the project log.

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Re:A small Lisp-Machine in an FPGA by pryelluw on Saturday February 11, 2017 @02:36PM (#13624304)

Could you link to an example?

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Re:A small Lisp-Machine in an FPGA by gluggymug on Saturday February 11, 2017 @05:25PM (#13625211)

There's only one example there. http://www.aviduratas.de/lisp/lispmfpga/code.html

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Re:A small Lisp-Machine in an FPGA by pryelluw on Saturday February 11, 2017 @06:04PM (#13625392)

Thank you.

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Re:A small Lisp-Machine in an FPGA by zump on Saturday February 11, 2017 @07:48PM (#13625876)

What's a really well written OSS Verilog example? Trying to switch from embedded to RTL design here.

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