I noticed whilst writing a verilog implementation - seeing the @PC+ relative modes for immediate data made me dig out my PDP-11 reference card.
The number of addressing modes has been halved, gaining a bit for register encoding, and the status register is now in the register file (R2), and R3 is used to generate various constants depending on mode.
I noticed whilst writing a verilog implementation - seeing the @PC+ relative modes for immediate data made me dig out my PDP-11 reference card.
The number of addressing modes has been halved, gaining a bit for register encoding, and the status register is now in the register file (R2), and R3 is used to generate various constants depending on mode.
Compare and contrast:
* https://en.wikipedia.org/wiki/PDP-11_architecture#CPU_regist... * https://en.wikipedia.org/wiki/TI_MSP430#MSP430_CPU