Re:RISC-V port accepted for inclusion in GCC
by zhemao on Wednesday January 18, 2017 @06:44PM
(#13431595)
I assume you are referring to SiFive's HiFive board. It's certainly a great accomplishment. I'm actually a Ph.D. student in the UC Berkeley lab that produced the RISC-V ISA and interned at SiFive over the summer. I've worked on the RocketChip SoC generator they used to produce the RISC-V processor on that board. So I definitely want them to succeed.
But there is still a very long way to go. Clock speed is not the only determinant of processor performance. Even low end laptops like the ARM-based Chromebook have out-of-order processors. The Rocket CPU used in the HiFive board is an in-order machine. There is an out-of-order implementation called BOOM, but it is not quite as mature. Whereas Rocket has been taped out and validated many times in our Berkeley test chips and now in SiFive's commercial silicon, BOOM has not yet been taped out.
And I'll be the first to admit that RocketChip is not nearly as reliable as you would like for a consumer product. SiFive's done a lot of work to improve the system, but there are probably still outstanding bugs in the memory system.
It depends. If you want something like Opera or Firefox it won't run at all. If you are satisfied with basic functionality then you can use browsers like w3m which work well on low-powered devices. I think some developers will find a good compromise between performance and functionality.
And by the way, the very first R5 already runs with 320 MHz :-)