Re:TensorFlow machine learning now optimized for the Snapdra...
by pjscott on Thursday January 12, 2017 @02:41AM
(#13380524)
Looks like those slides are for an older version. Since then they've bumped up the size of the vector execution units from 64 bits to 1024 bits and quadrupled the number of them, if I'm reading this right.
http://www.anandtech.com/show/10948/qualcomm-snapdragon-835-...
TensorFlow does lots of matrix multiplies. The Hexagon chip can do 8 multiplies each cycle, and runs multiple threads on each core. The benchmark isn't clear, but it's likely that _one_ Hexagon instruction can replace multiple normal ARM instructions for the inner loop.
You can see some more on how the Hexagon DSP works here: http://pages.cs.wisc.edu/~danav/pubs/qcom/hexagon_hotchips20...