Re:I've been writing ring buffers wrong all these years
by tbirdz on Wednesday December 14, 2016 @01:56PM
(#13178636)
>iterating backward through memory is horrific for cache performance
This isn't true for Intel chips since Netburst Pentium 4. The hardware prefetchers can handle predicting iterating through an array forwards, backwards, and even strided accesses [0]. The arrays takes up the same number of cache lines in both cases, so going forwards or backwards are still going to have the same number of cache misses.
This isn't true for Intel chips since Netburst Pentium 4. The hardware prefetchers can handle predicting iterating through an array forwards, backwards, and even strided accesses [0]. The arrays takes up the same number of cache lines in both cases, so going forwards or backwards are still going to have the same number of cache misses.
0: https://software.intel.com/en-us/articles/optimizing-applica...