It it is one of those interesting metrics, or one I came across researching the Cortex-M which is that at modern process node geometries the CPU part of a Cortex-M chip (not including all of the on chip peripherals, RAM, and Flash) easily fits inside the bond pad of an 8080A. As the 8080A had 40 pins that is 40 Cortex-M CPUs in silicon that Intel "threw away" by depositing a square of gold on the silicon.

But in terms of documentation that is related directly to the transistors, it would be interesting to evaluate number of lines of VHDL to the number of inferred transistors. I know you get a report after you have finished place and route on your typical work flow but has anyone rolled that up to "2.5 lines of VHDL per 100 transistors" or something?