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Re:X86 Register Encoding by pcwalton on Tuesday November 01, 2016 @03:03PM (#12849095)
The binary sizes are also similar when I last measured. Keep in mind that (a) ARM and AArch64 have quite a few addressing modes as well; (b) ARM has things like LDMIA/STMDB and AArch64's LDP/STP that compress function prologs and epilogs; (c) more registers means you don't have to spill as much; (d) three address instructions are often more compact than a MOV plus a two address instruction, which helps with typical register allocation algorithms.
Re:X86 Register Encoding by mikeash on Tuesday November 01, 2016 @03:54PM (#12849514)
Thanks for the info, to you and all the other replies!