I haven't seen hardly any FPGA users or experts review it.
There are fair number of these sorts of languages out there. Currently I'm using Altera's OpenCL kit which certainly falls into this high level design category.
The thing is that even if you're coding in a language that looks like C, you need to understand how hardware is inferred from it. Which requres a basic understanding of hardware concepts like state machines built from combinational logic and flip flops, as well as pipelining.
Bottom line on high level design... Plus side; gloss over details, focus on the workload. Down side; weird idioms, extra overhead compared to low level (i.e. Verilog).
If you have to write stilted HLL to implement your design anyway, you might as well do it properly and write it in one of the HDLs instead.
However, there is little incentive for FPGA manufacturers to publish enough details for open FPGA compilers to be developed.
Unlike CPUs that can present a public ISA and handle fancy microarchitecture details behind the scenes, FPGA compilers require intimate knowledge of the particular FPGA's microarchitecture. No need to spill the secret sauce.
Also, when you target an FPGA, you target a single FPGA model. Change to a different model even in the same produce family you must recompile. BTW, for large FPGAs compilation can take all night.
And lastly, FPGA compilation is a graph embedding problem which is significantly more difficult that the sequential optimization problem CPU compilers handle. This is why it takes so long to compile for FPGA.