Google's “Director of Engineering” Hiring Test

Re:Google's “Director of Engineering” Hiring Test by gcp on Thursday October 13, 2016 @04:21PM (#12703725)

Popcnt isn't particularly well optimized in most micro-architectural implementations.

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Re:Google's “Director of Engineering” Hiring Test by mitchty on Thursday October 13, 2016 @05:31PM (#12704215)

Looks that way with a quick test. But it looks like there may be a better way with SSE3 PSHUFB: http://wm.ite.pl/articles/sse-popcount.html

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Re:Google's “Director of Engineering” Hiring Test by rayiner on Thursday October 13, 2016 @05:45PM (#12704321)

Is it? It looks like on most recent Intel CPUs, it's 3 cycle latency, 1 cycle throughput on a 64-bit register. A 8-bit LUT solution is going to less than 16-bits per cycle on any recent Intel/AMD CPU (maximum of two load ports).

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Re:Google's “Director of Engineering” Hiring Test by gcp on Thursday October 13, 2016 @06:21PM (#12704597)

Hmm, much better than I remember. I guess this goes a long way to explain why this wasn't always seen in practice: http://danluu.com/assembly-intrinsics/

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