Re:Epiphany-V: A 1024-core 64-bit RISC processor
by AnimalMuppet on Wednesday October 05, 2016 @03:43PM
(#12647101)
In fact, you have two trade-offs. One is what you said - that for a fixed amount of memory, the more cores, the less memory you have per core. The second trade-off is the transistor budget - the more space you use for cores, the less space you have left for memory.
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Re:Epiphany-V: A 1024-core 64-bit RISC processor
by FullyFunctional on Wednesday October 05, 2016 @07:23PM
(#12648837)
The third trade off is cycle time; the larger the memory, the longer it takes to access it. This is why L1 caches are typically 16-64 KiB and despite that access is typically 2-3 cycles. However, 3+ cycles is difficult to hide in an in-order processor like this.