I was taking a bit of poetic license there; what I meant is that the ABI that the GPU presents to the CPU contains a number of high-level instructions that must be further decoded within the GPU, in the same way that modern "CISC-presenting" processors decode CISC ops into RISC μops.

That's only for graphics programming, mind you; the GPGPU interface is pretty directly representative of the GPU's internal RISC execution strategy.