The usual term is strong versus weak memory models. In x86 and SPARC (TSO), the only reordering in hardware that you can do is having reads complete before pending writes--all writes happen in order, all reads happen in order, and a pending read must complete before a pending write can. Other architectures allow much more reordering at the hardware level.

If you know the C++11 memory model, x86 and SPARC (TSO) basically make all memory loads implicitly atomic release/acquire. In contrast, most machines follow something akin to release/consume (the DEC Alpha famously has a basically broken memory model that allows *p to complete before p).