Re:Fujitsu Switches Horses for Post-K Supercomputer, Will Ri...
by bogomipz on Friday July 01, 2016 @07:40PM
(#12020486)
When you say "raw ISA" and "underlying VLIW code"are you referring to the microcops/mirocde or is this something specific to ARM chips?
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Re:Fujitsu Switches Horses for Post-K Supercomputer, Will Ri...
by monocasa on Friday July 01, 2016 @09:05PM
(#12020899)
I'm talking about IBM's DAISY, Transmeta's Crusoe, and Nvidia's Denver. These are more or less fairly standard VLIW machines that are designed to only run a JIT compiler for another machine architecture (PowerPC, x86, and ARM respectively). This JITed code is the only other code running on the machine, so they basically look like native versions of the architectures they emulate.
Edit: These machines also do a lot of cool stuff under the hood. DAISY's native binary format looks more like a CFG than we pure instruction steam. The Crusoe has some really sweet exposed speculation hardware. I'm sure Denver does some really cool stuff too, there's just not a whole lot of publicly available information on it.
Re:Fujitsu Switches Horses for Post-K Supercomputer, Will Ri...
by bogomipz on Saturday July 02, 2016 @01:33AM
(#12021511)
Ah neat, I think I remember hearing about the transmeta one back when. These weren't terribly successful though right?
What is the acronym "CFG", I wasn't able to find that anywhere.