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Re:Fujitsu Switches Horses for Post-K Supercomputer, Will Ri... by trsohmers on Friday July 01, 2016 @04:14PM (#12019325)
Going through them would be a book in itself (The ARMv8 reference manual is itself a couple thousand pages, which I have only gone through a fraction of). I think RISC-V is the closest thing to what I would like in a simple general purpose ISA, even though it is not perfect (no branch delay slots, no post modifies/register writebacks, don't like the immediate encoding). It is a hell of a lot better than the mess ARM made, and the basic (IMAFD) instruction reference can be kept to a single page ;)
Re:Fujitsu Switches Horses for Post-K Supercomputer, Will Ri... by stephencanon on Friday July 01, 2016 @05:53PM (#12019963)
> no branch delay slots

We fought that battle 15 years ago, and delay slots lost (for general-purpose CPUs).

Re:Fujitsu Switches Horses for Post-K Supercomputer, Will Ri... by rayiner on Friday July 01, 2016 @05:02PM (#12019624)
Wait you like branch delay slots?!
Re:Fujitsu Switches Horses for Post-K Supercomputer, Will Ri... by trsohmers on Friday July 01, 2016 @05:24PM (#12019763)
I love branch delay slots, and they are a key feature for getting highest performance in the architecture I am working on... if you have things like guaranteed latency and static scheduling (like we do with the REX Neo architecture), delay slots are VERY useful in tight loops. I understand not including them in a general purpose design with branch prediction, but I'm not a fan of branch prediction and its effects on determinism.
Re:Fujitsu Switches Horses for Post-K Supercomputer, Will Ri... by coderjames on Saturday July 02, 2016 @11:49AM (#12022923)
I'd never heard of the Rex Neo until your post. Looks very interesting!