Re:Nyuzi: An experimental FPGA multicore GPGPU processor
by sklogic on Wednesday March 30, 2016 @05:22PM
(#11393118)
> If it's Python, it's not a DSL by definition.
Scala is not any better. It's exactly the same kind of a eDSL - no macros, nothing, just generating objects in runtime and then serialising this tree into a Verilog code. Nothing fancy.
> around state machines
What state machines?!? It does not have any more features for defining FSMs than an underlying Verilog.
Scala is not any better. It's exactly the same kind of a eDSL - no macros, nothing, just generating objects in runtime and then serialising this tree into a Verilog code. Nothing fancy.
> around state machines
What state machines?!? It does not have any more features for defining FSMs than an underlying Verilog.