So there's really no legitimate way to insist that Moore's law has to refer to the lowest cost number of transistors. It actually wasn't that by coinage and it certainly isn't that by common usage. I've even got a copy of a memo by Moore in my 6.175 lecture notes endorsing a broader conception of Moore's law.
Now, if you're in the weeds of designing a chip or node, yeah, things like feature size are paramount, but why are you going to the trouble of moving to a new node in the first place, especially with the end of Dennard scaling a decade+ ago? Power consumption could be an alternative to the raw economics, or maybe taking up less space in the smaller mobile form factors. Intel's leading with mobile chips for some reason.
(I have old and myopic eyes so I don't do mobile devices and didn't know of such obvious in retrospect tricks. Another thing to push me to getting a cheap smartphone to replace my ancient Nokia candybar feature phone.)
Moore's law is stated in terms of a doubling of lowest cost transistors you can fit on a wafer, and results in massive yield gains if you shrink an existing design when moving from node to node (the "tick" in Intel's tick-tock cycle). So whatever customers want, you'll still move to the next node if the economics allow you to deliver the same at a lower cost. This is one of the things that drives game console economics, mid-life refreshes which allow delivering the same capabilities with cheaper and fewer chips (fewer decreases other manufacturing costs).
The heat problem and related end of "free" speed increases is due to the failure of Dennard scaling (https://en.wikipedia.org/wiki/Dennard_scaling) after a good 30 year run.
Every time the scale is halved, manufacturers need a whole new generation of ever more precise photolithography machines. Building a new fab line today requires an investment typically measured in many billions of dollars — something only a handful of companies can afford.
Ignoring the far out scaling limits, this is what I would have focused on. As far as I can tell, the biggest issue right now is the skyrocketing costs of lithography due to the multiple masks required for multiple patterning (https://en.wikipedia.org/wiki/Multiple_patterning).
If, and it's a big if (see Intel continuing to push out they date they plan to adopt it), when EUV lithography become practical that should change this very recent economic issue, substituting manufacturing costs in buying and running $$$ EUV machines for many fewer masks required for each design, lowering non-recurring engineering (NRE) expenses.
That could return a lot of the game to what it was like for a long time, albeit with only a very few foundries being able to afford these machines. The first generation the leading company in the Netherlands is trying is pretty insane in how they generate the light, by exciting tin vapor (!), imagine the inherent contamination potential for both the focusing optics and the wafer....
One other detail: to the extent a lot of companies start focusing on the economic ~22nm or so node that's just before costs skyrocket, we may be seeing some serious economies of scale as people focus on aspects other than the design shrink. Sure, you'd like smaller nodes, especially for lowest power applications, note how Intel is leading with mobile SKUs for it's newest smaller node chips, but that node is perfectly fine for a whole lot of things. Another economic factor to focus on, not everyone is an Intel, nVidia, Apple etc. that needs cutting edge nodes.