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A comment on Why I will be using RISC-V in my next chip. Parent comment

Re:Why I will be using RISC-V in my next chip by _chris_ on Saturday January 09, 2016 @07:24PM (#10873531)
The studies I've seen have shown that the FU mix is heavily skewed and changing on every basic block, particularly when you offload the DLP to a more efficient vector/SIMD unit.

I'm not sure I see how MT would solve the mix problem, if each thread gets an issue cycle (and each thread itself has a bad mix).

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Re:Why I will be using RISC-V in my next chip by protomyth on Saturday January 09, 2016 @07:32PM (#10873554)
I was just thinking that the the bad mixes might on average fill in the gaps to what the processor actually had for resources.
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Re:Why I will be using RISC-V in my next chip by creshal on Saturday January 09, 2016 @07:46PM (#10873598)
Even GPUs, which have arguably far more predictable instruction mixes, struggled massively to get a useful utilization on VLIW architectures – AMD tried two different ones from 2006 to 2011 before they finally gave up on the concept and started using RISC architectures like Nvidia had been using all the time.
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