The answer to the second unasked question is, if cost were no barrier, then the lower bound for our current class of tech is almost certainly an effective feature size of ~1.5nm, or about 5 or 6 generations. When I'm feeling bullish (usually after talking to my boys at Intel) I feel confident we'll eventually see 3nm. I suspect something more exotic will intercept by then, and carry after that in effective feature size reduction. Of course, by then, my hot-air-lifting-body-balloon unicorn will have realized, so I won't care =)
Since there's more than just silicon to a chip, those features can often be of metallic atoms, which can be smaller than Si, and hence more than 20 atoms wide.