Minor nitpick: There is no such thing like fetching a cache line from another core, at least in Intel x64 architecture. All the synchronizing between the cores happen at L3 cache layer and QPI, because caches are inclusive and L3 is common to all cores. When a core writes to L3, it invalidates the same cache line in L1 and L2 caches of other cores. Therefore if your cores write to the same cache line, you have a big problem regardless of the chosen memory order model.