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Re:Souper – A Superoptimizer for LLVM IR by ingenter on Wednesday October 28, 2015 @05:35AM (#10463468)
I wonder if it's possible to do a similar thing for codegen. i.e. generate more efficient code based on SMT solver and CPU model.
Re:Souper – A Superoptimizer for LLVM IR by joajoa on Wednesday October 28, 2015 @07:58AM (#10463895)
Absolutely. See [1] for instance. Superoptimization has been around since the 80s and at the first superoptimizer by Alexia Massalin targeted the 68000 instruction set.

[1] http://superoptimization.org/w/images/f/f1/Wp4.pdf

Re:Souper – A Superoptimizer for LLVM IR by cwzwarich on Wednesday October 28, 2015 @07:57AM (#10463892)
It's been done:

http://theory.stanford.edu/~aiken/publications/papers/asplos...

They had to restrict themselves to instruction sequences of length 3 due to limited resources, and say that to go beyond instruction sequences of length 4 they would need a better approach.

Re:Souper – A Superoptimizer for LLVM IR by fulafel on Wednesday October 28, 2015 @08:02AM (#10463907)
This has been done in '87 by Massalin: https://www.cs.arizona.edu/~collberg/Teaching/553/2011/Resou...

(both are brute force though, not solver-based)

Re:Souper – A Superoptimizer for LLVM IR by cwzwarich on Wednesday October 28, 2015 @08:16AM (#10463960)
Massalin's superoptimizer required humans to check the correctness of optimizations. It also didn't generate parameterized peephole optimizations; it directly optimized concrete instruction sequences.
Re:Souper – A Superoptimizer for LLVM IR by DannyBee on Wednesday October 28, 2015 @10:23AM (#10464593)
Yes, there are tons of papers on doing optimal scheduling/instruction selection/register allocation by using integer linear programming.

Modeling is not even the hard part, it's modeling in a way that doesn't take till the heat death of the sun to solve ;-)

Re:Souper – A Superoptimizer for LLVM IR by andrewchambers on Wednesday October 28, 2015 @06:23AM (#10463610)
I want to see efficient backends automatically generated from a flat list of assembly instruction descriptions using similar methods.