The actual verilog is often the easy part. Writing a good simulation (see testbench.v and the firmware folder) to make sure that verilog does what you expect takes a fair amount of work. Getting the verilog to synthesize and meet timing is also another large piece of the work. It appears that (unlike a lot of FPGA projects) the author of this has actually written scripts to automate that part, but you can bet there was a fair amount of trial and error to get those scripts correct. There's always a lot of "fighting the tools" involved in this process.