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Re:Branch Prediction and the Performance of Interpreters – D... by vardump on Monday August 10, 2015 @06:44AM (#10033744)
Right, I also do work in embedded (without OS), so I'm familiar with the limitations. However, there are situations where it's tempting to write a very primitive JIT or at least glue pieces of code together in a buffer and execute it, to get good inner loop performance by making it as few instructions as possible.

So far C has been enough. Achieving low (=preferably none) defect rate using C is challenging enough.

Usually FPGAs can take care of performance critical part. They do increase total cost, though.

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