Re:Branch Prediction and the Performance of Interpreters – D...
by sklogic on Monday August 10, 2015 @05:58AM
(#10033607)
There are architectures that require manual pipeline control. MIPS, for example, or any VLIW architecture (including many of the modern GPUs). Cache is also often programmable (see scratch memory in Sparc, local memory in GPUs, etc.)
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