quinta1k
Re:Verilog sources for Western Digital's open source RISC-V core
on Sunday January 27, 2019 @03:06AM (#19010848)
This was clear 10 years ago when ee and cs salaries started diverging significantly and ee companies remained fairly stingy, even with food and drinks and perks at the workplace, let alone salaries.
It will end up costing them faaaar more than the salaries and benefits that were saved. Gg
Re:Verilog sources for Western Digital's open source RISC-V core
on Sunday January 27, 2019 @02:25AM (#19010732)
Supply and demand. FANGs vertical integration. No more Moore.
Re:Verilog sources for Western Digital's open source RISC-V core
on Sunday January 27, 2019 @02:20AM (#19010719)
Top tiers. Proportions
Re:Verilog sources for Western Digital's open source RISC-V core
on Saturday January 26, 2019 @10:45PM (#19010250)
It would be their dream come true if the hw oss community (very small) takes this up and develops it into something huge like for sw projects. There is so much manpower needed to develop these kinds of things - what better way than oss.
However, too little, too late, ee industry. An entire generation of top tier college students have pretty much skipped ee.