mupuf
I fixed up quite a few things based on it! I'll keep on working on the code and hopefully will have some more tangible to share at the end of the summer :)
In the case of FPGA boards, OSHW would thus require "mechanical drawings, schematics, bills of material, PCB layout data, and integrated circuit layout data" given that no HDL source code is present in it.
Seems like I have been a little loose in my description, but at least I did not completely miss the point. Accuracy is however needed, I'll try to find another formulation or link to the pages you sent for people to see that it is a little more complex!
Open toolchains are another topic, and indeed, Lattice FPGAs are now super attractive because of it! Hopefully, project X-Ray will bear fruits soon and I can ditch Vivado, at least during development!
In the end, a hardware design using Lattice or Xilinx FPGAs is not more or less open. Discrete components will always be proprietary (unless your name is Sam Zeloof). What matters is pushing the boundary further and further, and for this, FPGAs are amazing!
Thanks for the feedback, I'll make some changes to clarify my thoughts!
The point of LiteDIP is to provide both the IPs, and their drivers.
Also, rather than needing IPs to be located at a certain address in any sort of bus (PCI BARs, wishbone, ...), litedip exposes the list of IPs starting at address 0 along with their version and relative address.
The driver then lists these blocks, and either has a driver for this block's version or not.