ispiansclsda

It is interesting that one can write code (for which certain computational/logic structures are automatically inferred) describing hardware to run inference models, while inferring that such a piece of computing power will be useful to infer the future.

The funniest part is that people would lose their minds if this happened to a Picasso.

Alexa, play Despacito.

Dang: typo. Should be "Where in the World Is Danmark's $2B?"

Humans literally are not good enough at biochemistry to have created Zika.

> When this happens, the chip could short-circuit power lines

No chip design would ever do this. The chip would incinerate itself.

> superimpose a signal on the power-lines to notify the rest of the system

The rest of the system i.e. the BMC already know that something weird is up.

> the simplest action for a chip on the SPI bus would be to hold the MISO line low during power on

MISO is master-in, slave-out for anyone not familiar with serial peripheral interface jargon. Usually, the slave quad-SPI memory would send the configuration over this line, so pulling it low should dump the real data to ground.