Gebetto

I have a background in Electrical Engineering, and when coding in a hardware description language, I feel that instantiating and connecting entities is like drawing a hierarchical schematic but in text mode. And writing the RTL implementation of an entity is like giving requirements to the synthesis tools that I need a bunch of gates and flip flops that implement this functionality. When coding in some programming language, I have a completely different mindset.

Programming usually means coding in some language that will be compiled to machine language, and hardware description is so different kind of "programming" that I think it's dangerous to call it programming at all.

Why do they sometimes include other signals than clock and asynchronous reset/set in sequential process sensitivity lists? For example D in Listing 6.2. The extra signals in the sensitivity list don't add any functionality, and might be confusing to the reader.

It's probably good to teach the two process FSM first, because it resembles the mathematical model, but back when I did VHDL design, I found single process FSMs more straightforward. Can't remember what they looked like exactly, but something like Thompson's answer here: http://stackoverflow.com/questions/5961751/encoding-state-ma...