CorrectHorseBat

Is it? Here I read it's gotten much worse. Now you have 3 minutes to escape a fire while 40 years you had 17 minutes. (Other things have gotten better of course)

Which is not going to happen in the upcoming years

I've read the exact opposite, vendors are reducing the standard from 16GB back to 8GB

15 fold increase in price and still only 15 cents per kg, that is insane.

I see this praise of tcl/tk a lot on HN, but everyone I know (myself included) absolutely hate working with it in VLSI CAD tools.

2G is being shutdown (or already has) in many countries and those old phones and core services will need to be replaced.

Hydraulic rim brakes also exist and they are amazing too

How about just leaving it on 24h time all the time?

Hardware companies are notoriously bad at software. The software they use sucks, the languages they use suck, the internal tooling software they write sucks.

They don't know what good developer experience is, how do you expect them to deliver it to other people?

>Schrödinger's China at once is an evil entity looking to use AI for their own nefarious purposes yet also willing to cooperate with their main competitor to prevent other actors (who??) from achieving similar goals (all while under a chip embargo too!!)

I don't see the contradiction, even if China is evil, why would they want others to be able to do the same thing?

The USA and USSR also signed the Partial Nuclear Test Ban Treaty during the height of the cold war.

There's also information in the compiler and the zip binary, without that I'm pretty sure it's not possible.

KVM has a much larger attack surface than Xen

Chinese is also written left to right

If you prefer the term person to avoid confusion, fine by me. But then also don't use the term "experimenting on humans", because the meaning of that is experimenting on persons against their will.

There is nothing extra magical about conception that makes the creation of a human (or a person if you prefer that), all of the DNA already existed before and nothing that defines a person is yet present.

Testing on early stage embryos is a thing yes. They have no brain, no heartbeat, feel no pain. Yes, they could potentially develop into a human being, but I wouldn't call it a live human yet. I understand your repulsion, but to other people it's no different than testing on sperm, eggs or other human tissues. And as the other guy said, these were discarded embryos from IVF, they would never become humans.

Here in Belgium it's the other way around. we've had IPv6 for over 10 years for basically all home internet, but mobile is still ipv4 only. Not sure why since it's all the same companies.

No Korea and Japan? Aren't most of the big non-Chinese battery companies Korean and Japanese?

It is far from solved in IC, synthesis tools sometimes still do really stupid things and there's still quite a lot of hand-holding required to get to a working chip.

I can't imagine humanity, let alone any company or the stock market survive runaway AI.

Median doesn't say anything about the extremes and income isn't wealth.

Bicycle bells can be used to warn other cyclists

Real hardware has clock trees. Wouldn't all (most?) problems with delta cycles go away if the HDL understood the concept of clocks and clock balancing?

In a way is further away, but in another way it's actually closer to how real hardware works: Clock (and reset) trees are real physical things which exist on all digital chips.

Is it really if you restrict yourself to sensible design practices? You generally want to simulate simple clocked Logic with a predefined clock, most of the time anything else is a mistake or bad design. So just if rising edge clk next_state <= fn(previous_state, input) . It seems to me VHDL and verilog are simply at the wrong abstraction level and by that they make simulation needlessly complicated and design easy to do wrong. To me it seems that if they had the concept of clocks instead none of this would be necessary and many bugs avoided (but I'm no expert on simulator design, so I might be missing something...)

I'm not sure if you are trolling. 99.999% of digital design is "if rising edge clk new_state <= fn(old_state, input)", with an (a)sync reset. The language should make that the default and simple to do, and anything else out of the ordinary hard. Now it's more the other way around.

Those are analog circuits, if you put them in your digital design you are doing something wrong.

The real question is, why do we even need this? Why don't VHDL and Verilog just simulate what hardware does? Real hardware doesn't have any delta cycles or determinism issues due to scheduling. Same thing with sensitivity lists (yes we have */all now so that's basically solved), but why design it so that it's easy to shoot in your own foot?

Don't you need to register and actively defend you trademark for it to apply?

I think we'll be soon at the point where articles are written by asking AI to extend a three point bullet list to 30 pages, and read by asking AI to summarize articles into a three point bullet list.

Another possible benefit I've heard of is it can stop some kinds of voter intimidation:

Someone gets hand of an empty ballot, they fill in the ballot and give it to you and tell you to come back with another empty ballot. Rinse and repeat. Of course, with today's smartphones there are simpler ways to do this. Also moot if you can vote by mail, which is why voting by mail is a really bad idea.